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19-3014; Rev 2; 3/09
Dual Per-Pin Parametric Measurement Units
General Description
The MAX9949/MAX9950 dual parametric measurement units (PMUs) feature a small package size, wide force and measurement range, and high accuracy, making the devices ideal for automatic test equipment (ATE) and other instrumentation that requires a PMU per pin or per site. The MAX9949/MAX9950 force or measure voltages in the -2V to +7V through -7V to +13V ranges, dependent upon the supply voltage (VCC and VEE). The devices handle supply voltages of up to +30V (VCC to VEE) and a 20V device under test (DUT) voltage swing at full current. The MAX9949/MAX9950 also force or measure currents up to 25mA with a lowest full-scale range of 2A. Integrated support circuitry facilitates use of an external buffer amplifier for current ranges greater than 25mA. A voltage proportional to the measured output voltage or current is provided at the MSR_ output. Integrated comparators, with externally set voltage thresholds, provide detection for both voltage and current levels. The MSR_ and comparator outputs can be placed in a highZ state. Integrated voltage clamps limit the force output to levels set externally. The force-current or the measure-current voltage can be offset -0.2V to +4.4V (IOS). This feature allows for the centering of the control or measured signal within the external DAC or ADC range. The MAX9949D/MAX9950D feature an integrated 10k force-sense resistor between FORCE_ and SENSE_. The MAX9949F/MAX9950F have no internal force-sense resistor. These devices are available in a 64-pin 10mm x 10mm, 0.5mm pitch TQFP package with an exposed 8mm x 8mm die pad on the top (MAX9949) or the bottom (MAX9950) of the package for efficient heat removal. The exposed paddle is internally connected to V EE. The MAX9949/MAX9950 are specified over the commercial (0C to +70C) temperature range.
Features
o Force Voltage/Measure Current (FVMI) o Force Current/Measure Voltage (FIMV) o Force Voltage/Measure Voltage (FVMV) o Force Current/Measure Current (FIMI) o Force Nothing/Measure Voltage (FNMV) o Five Programmable Current Ranges 2A 20A 200A 2mA 25mA o -2V to +7V Through -7V to +13V Input Voltage Range and Higher (Up to 20V Voltage Swing at Full Current) o Force-Current/Measure-Current Voltage Offset (IOS) o Programmable Voltage Clamps for the Force Output o Low-Leakage, High-Z Measure State o 3-Wire Serial Interface o Low Power, 8mA (max) per PMU
MAX9949/MAX9950
Ordering Information
PART MAX9949DCCB+ MAX9949FCCB+ MAX9950DCCB+ MAX9950FCCB+ TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 64 TQFP-EPR* 64 TQFP-EPR* 64 TQFP-EP** 64 TQFP-EP**
Applications
Memory Testers VLSI Testers System-on-a-Chip Testers Structural Testers
+Denotes a lead(Pb)-free/RoHs-compliant part. *EPR = Exposed pad on top. **EP = Exposed pad on bottom. Note: Exposed pad is internally connected to VEE.
Selector Guide
PART MAX9949DCCB+ MAX9949FCCB+ MAX9950DCCB+ DESCRIPTION Internal 10k force-sense resistor No internal force-sense resistor Internal 10k force-sense resistor No internal force-sense resistor
Pin Configurations appear at end of data sheet.
MAX9950FCCB+
________________________________________________________________ Maxim Integrated Products
1
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
ABSOLUTE MAXIMUM RATINGS
VCC to AGND .......................................................................+20V VEE to AGND.........................................................................-15V VCC to VEE ...........................................................................+32V VL to AGND............................................................................+6V AGND to DGND.....................................................-0.5V to +0.5V All Other Pins ...................................(VEE - 0.3V) to (VCC + 0.3V) Digital Inputs/Outputs ...................................-0.3V to (VL + 0.3V) Continuous Power Dissipation (TA = +70C) 64-Pin TQFP-EP (derate 43.5mW/C above +70C)....3478mW JA (Note 1) ................................................................+23.0C/W JC (Note 1) .....................................................................+8C/W Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Operating Temperature (commercial) Range ........0C to +70C Lead Temperature (soldering 10s) ..................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +12V, VEE = -7V, VL = +3.3V, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER FORCE VOLTAGE (Note 3) Force Input Voltage Range VIN0_, VIN1_ DUT current at full scale DUT current = 0 Input Bias Current Forced-Voltage Offset Error Forced-Voltage Offset Temperature Coefficient Forced-Voltage Gain Error Forced-Voltage Gain Temperature Coefficient Forced-Voltage Linearity Error MEASURE CURRENT (Note 3) Measure-Current Offset Measure-Current Offset Temperature Coefficient Measure-Current Gain Error Measure-Current Gain Temperature Coefficient Linearity Error Measure Output Voltage Range over Full Current Range (Note 8) IMLER TA = +25C, gain, offset, and common-mode errors calibrated out (Notes 4, 5, 6) VIOS = VDUTGND VIOS = 4V + VDUTGND Ranges A-D Range E -0.02 -1 -4 0 IMGE TA = +25C (Note 7) -1 20 +0.02 +1 +4 8 IMOS TA = +25C (Note 4) -1 20 +1 +1 %FSR ppm/C % ppm/C %FSR nA V VFLER TA = +25C, gain and offset errors calibrated out (Notes 4, 5) -0.02 VFGE TA = +25C, nominal gain of +1 -1 VFOS TA = +25C -25 100 0.005 10 +0.02 +1 VCC = +12V, VEE = -7V VCC = +18V, VEE = VEE + 3.5V -2 -7 VEE + 3.5V 1 +25 VCC 3.5V +7 +13 VCC 3.5V A mV V/C % ppm/C %FSR V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Forced Voltage
VDUT
VMSR
2
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Dual Per-Pin Parametric Measurement Units
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -7V, VL = +3.3V, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER Current-Sense Amp Offset Voltage Input Rejection of Output Measure Error Due to Common-Mode Sense Voltage SYMBOL VIOS CONDITIONS Relative to VDUTGND Specified as the percent of full-scale range change at the measure output per volt change in the DUT voltage Range E, R_E = 1M Range D, R_D = 100k Measure Current Range Range C, R_C = 10k Range B, R_B = 1k Range A, R_A = 80 FORCE CURRENT (Note 3) Input Voltage Range for Setting Forced Current Over Full Range Current-Sense Amp Offset Voltage Input VIOS Input Bias Current Forced-Current Offset Forced-Current Offset Temperature Coefficient Forced-Current Gain Error Forced-Current Gain Temperature Coefficient Forced-Current Linearity Error IFLER TA = +25C, gain, offset, and common-mode errors calibrated out (Notes 4, 5, 6) Ranges A-D Range E -0.02 -1 +0.001 -2 -20 -200 -2 -25 -25 100 VMGER TA = +25C, nominal gain of +1 -1 0.005 10 +1 IFGE TA = +25C (Note 7) -1 20 +0.02 +1 +0.007 +2 +20 +200 +2 +25 +25 mA A IFOS TA = +25C (Note 4) -1 20 +1 VINI VIOS VIOS = VDUTGND VIOS = 4V + VDUTGND Relative to VDUTGND -4 0 -0.2 1 +1 +4 +8 +4.4 V V A %FSR ppm/C % ppm/C %FSR nA %FSR/V -2 -20 -200 -2 -25 MIN -0.2 TYP MAX +4.4 UNITS V
MAX9949/MAX9950
CMVRLER
0.001
0.007 +2 +20 +200 +2 +25
%FSR/V
A
mA
Rejection of Output Error Due to Common-Mode Load Voltage
CMRIOER
Specified as the percent of full-scale range change of the forced current per volt change in the DUT voltage Range E, R_E = 1M Range D, R_D = 100k
Forced-Current Range
Range C, R_C = 10k Range B, R_B = 1k Range A, R_A = 80
MEASURE VOLTAGE (Note 3) Measure-Voltage Offset Measure-Voltage Offset Temperature Coefficient Gain Error Measure-Voltage Gain Temperature Coefficient VMOS TA = +25C mV V/C % ppm/C
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -7V, VL = +3.3V, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER Measure-Voltage Linearity Error SYMBOL VMLER CONDITIONS TA = +25C, gain and offset errors calibrated out (Notes 4, 5, 6) DUT current at full scale DUT current = 0V VCC = +12V, VEE = -7V VCC = +18V, VEE = -12V MIN -0.02 -2 -7 VEE + 3.5V -5 -45 +28 D option only 7.8 VEE + 3.5V -5 VEE + 3.5V TA = +25C -25 1 VCLLO_, VCLHI_ VEE + 3.4V VEE + 3.5V -100 5V logic Input High Voltage (Note 9) VIH 3.3V logic 2.7V logic Input Low Voltage (Note 9) Input Current Input Capacitance COMPARATOR OUTPUTS (Note 9) Output High Voltage Output Low Voltage High-Z State Leakage Current High-Z State Output Capacitance VOH VOL VL = +2.375V to +5.5V, RPUP = 1k VL = +2.375V to +5.5V, RPUP = 1k 1 6.0 VL - 0.2 +0.4 V V A pF VIL IIN CIN 5V and 3.3V logic 2.5V logic 1 3.0 +3.5 +2.0 +1.7 +0.8 +0.7 V A pF V VCC 3.4V VCC 3.5V +100 10 TYP MAX +0.02 +7 +13 VCC 3.5V +5 -28 +45 13.3 VCC 3.5V +5 VCC 3.5V +25 nA mA k V UNITS %FSR
Measure Output Voltage Range over Full DUT Voltage (VDUT) FORCE OUTPUT Off-State Leakage Current Short-Circuit Current Limit Force-to-Sense Resistor SENSE INPUT Input Voltage Range Leakage Current COMPARATOR INPUTS Input Voltage Range Offset Voltage Input Bias Current VOLTAGE CLAMPS Input Control Voltage Clamp Voltage Range Clamp Voltage Accuracy DIGITAL INPUTS
VMSR
TA = +25C ILIMILIM+ RFS
V nA
V mV A
V V mV
4
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Dual Per-Pin Parametric Measurement Units
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -7V, VL = +3.3V, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER DIGITAL OUTPUTS (Note 9) Output High Voltage Output Low Voltage POWER SUPPLY Positive Supply Negative Supply Total Supply Voltage Logic Supply Positive Supply Current Negative Supply Current Logic Supply Current Analog Ground Current Digital Ground Current Power-Supply Rejection Ratio VCC VEE VCC - VEE VL ICC IEE IL IAGND IDGND PSRR No load, clamps enabled No load, clamps enabled No load, all digital inputs at rails No load, clamps enabled No load, all digital inputs at rails 1MHz, measured at force output 60Hz, measured at force output 20 85 +2.375 (Note 2) (Note 2) +10 -15 +12 -7 +18 -5 +30 +5.5 16.0 16.0 1.2 0.9 1.4 V V V mA mA mA mA mA dB VOH VOL IOUT = 1mA, VL = +2.375V to +5.5V, relative to DGND IOUT = -1mA, VL = +2.375V to +5.5V, relative to DGND VL 0.25 0.2 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9949/MAX9950
AC ELECTRICAL CHARACTERISTICS
(VCC = +12V, VEE = -7V, VL = +3.3V, CCM = 120pF, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER FORCE VOLTAGE (Notes 10, 11) Range E, R_E = 1M Range D, R_D = 100k Settling Time Range C, R_C = 10k Range B, R_B = 1k Range A, R_A = 80 Maximum Stable Load Capacitance FORCE VOLTAGE/MEASURE CURRENT (Notes 10, 11) Range E, R_E = 1M Range D, R_D = 100k Settling Time Range C, R_C = 10k Range B, R_B = 1k Range A, R_A = 80 Range Change Switching In addition to force-voltage and measurecurrent settling times, range A to range B, R_A = 80, R_B = 1k 480 50 35 20 25 10 s 45 s 2500 160 35 25 20 25 pF 30 s SYMBOL CONDITIONS MIN TYP MAX UNITS
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -7V, VL = +3.3V, CCM = 120pF, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER FORCE CURRENT (Notes 10, 11) Range E, R_E = 1M Range D, R_D = 100k Settling Time Range C, R_C = 10k Range B, R_B = 1k Range A, R_A = 80 FORCE CURRENT/MEASURE VOLTAGE (Notes 10, 11, 12) Range E, R_E = 1M Range D, R_D = 100k Settling Time Range C, R_C = 10k Range B, R_B = 1k Range A, R_A = 80 Range Change Switching In addition to force-voltage and measurecurrent settling times, range A to range B, R_A = 80, R_B = 1k CLMSR = 100pF CLMSR = 100pF, measured from 50% of digital input voltage to 10% of output voltage CLMSR = 100pF, measured from 50% of digital input voltage to 90% of output voltage 1000 1600 170 40 25 25 12 s 50 s 300 100 40 25 25 45 s SYMBOL CONDITIONS MIN TYP MAX UNITS
SENSE INPUT TO MEASURE OUTPUT PATH (Note 12) Settling Time MEASURE OUTPUT HIZ_ or HIZMSR True (0) to High-Z HIZ_ or HIZMSR False (1) to Active Maximum Stable Load Capacitance FORCE OUTPUT HIZFORCE True (0) to High-Z HIZFORCE False (1) to Active COMPARATORS 50mV overdrive, 1VP-P, CLCOMP = 20pF, RPUP = 1k measured from input-threshold zero crossing to 50% of output voltage (Note 13) CLCOMP = 20pF, RPUP = 1k measured from input-threshold zero crossing to 50% of output voltage CLCOMP = 20pF, RPUP = 1k, 20% to 80% Measured from 50% of digital input voltage to 10% of output voltage Measured from 50% of digital input voltage to 90% of output voltage 2 2 s s 250 ns 0.2 s
5
s
pF
Propagation Delay
75
ns
Rise Time Fall Time
60 5
ns ns
6
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Dual Per-Pin Parametric Measurement Units
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -7V, VL = +3.3V, CCM = 120pF, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise specified.) (Note 2)
PARAMETER DISABLE True (0) to High-Z SYMBOL CONDITIONS CLCOMP = 20pF, measured from 50% of digital input voltage to 10% of output voltage CLCOMP = 20pF, measured from 50% of digital input voltage to 90% of output voltage fSCLK tCH tCL tDO tCSS0 tCSH1 tCSH0 tCSS1 tDS tDH tCSWH tCSWL tLDW (Note 14) (Note 14) 10 22 0 5 10 0 10 10 20 500 12 12 22 MIN TYP 300 MAX UNITS ns
MAX9949/MAX9950
DISABLE False (1) to Active SERIAL PORT (VL = +3.0V, CDOUT = 10pF) Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Fall to DOUT Valid CS Low to SCLK High Setup SCLK High to CS High Hold SCLK High to CS Low Hold CS High to SCLK High Setup DIN to SCLK High Setup DIN to SCLK High Hold CS Pulse-Width High CS Pulse-Width Low LOAD Pulse-Width Low VDD High to CS Low (Power-Up)
100
ns
20
MHz ns ns ns ns ns ns ns ns ns ns ns ns s
Note 2: The device operates properly with different supply voltages with equally different voltage swings. Note 3: Tested at VCC = +18V and VEE = -12V. Note 4: Interpret errors expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point to end-point range, i.e., for the 25mA range, the full-scale range = 50mA and a 1% error = 500A. Note 5: Case must be maintained 5C for linearity specifications. Note 6: Current linearity specifications are maintained to within 700mV of the clamp voltages when the clamps are enabled. Note 7: Tested in range C. Note 8: Linearity of the measured output is only guaranteed within the specified current range. Note 9: The digital interface accepts +5V, +3.3V, and +2.5V CMOS logic levels. The voltage at VL adjusts the threshold. Note 10: Settling times are to 0.1% of FSR. Cx = 47pF. Note 11: All settling times are specified using a single compensation capacitor (Cx) across all current-sense resistors. Use an individual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges. Note 12: The actual settling time of the measured voltage path (SENSE_ input to MSR_ output) is less than 1s. However, the R-C time constant of the sense resistor and the load capacitance causes a longer overall settling time of the DUT voltage. This settling time is a function of the current-range resistor used. Note 13: The propagation delay time is only guaranteed over the force-voltage output range. Propagation delay is measured by holding the SENSE_ input voltage steady and transitioning THMAX_ or THMIN_. Note 14: Guaranteed by design.
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
Typical Operating Characteristics
(VCC = +12V, VEE = -7V, CL = 100pF, RL to +2.5V, range A: R_A = 80, RL = 180; range B: R_B = 1k, RL = 2.25k; range C: R_C = 10k, RL = 22.5k; range D: R_D = 100k, RL = 225k; range E: R_E = 1M, RL = 2.25M, TA = +25C.
TRANSIENT RESPONSE FVMI MODE RANGES A, B, C
MAX9949/50 toc01
TRANSIENT RESPONSE FVMI MODE RANGE D
MAX9949/50 toc02
TRANSIENT RESPONSE FVMI MODE RANGE E
MAX9949/50 toc03
0
IN_ 5V/div FORCE_ 5V/div
0
IN_ 5V/div FORCE_ 5V/div
0
IN_ 5V/div FORCE_ 5V/div
0
0
0
20s/div
100s/div
1.0ms/div
TRANSIENT RESPONSE FVMV MODE RANGE C
MAX9949/50 toc04
TRANSIENT RESPONSE FIMI MODE RANGES A, B, C
MAX9949/50 toc05
TRANSIENT RESPONSE FIMI MODE RANGE D
MAX9949/50 toc06
0
IN_ 5V/div MSR_ 5V/div
0
IN_ 5V/div
0
IN_ 5V/div
0
0
FORCE_ 5V/div
0
FORCE_ 5V/div
20s/div
20s/div
100s/div
TRANSIENT RESPONSE FIMI MODE RANGE E
MAX9949/50 toc07
IOS vs. POWER SUPPLIES
20 15 VCC 11.2
MAX9949/50 toc08
0
VOLTAGE (V)
IN_ 5V/div
10 5 0 -5 -10 -15 3.2 4.4 IOS (MAX) IOS (MIN) -0.2 VEE -7 1.8
0
FORCE_ 5V/div
1.0ms/div
8
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Dual Per-Pin Parametric Measurement Units
Pin Description
PIN MAX9950 1, 16, 33, 48 2, 15, 34, 47 3 4 5 6 7 8 9 10 11 12 13 14 17 18 19 20 21 22 23 24, 27 25 26 28 29 MAX9949 1, 16, 33, 48 2, 15, 34, 47 14 13 12 11 10 9 8 7 6 5 4 3 64 63 62 61 60 59 58 54, 57 56 55 53 52 NAME VEE VCC Negative Analog Supply Input Positive Analog Supply Input PMU-B Range-Setting-Resistor Common Connection. Connect to one end of all the rangesetting resistors (RB_) for PMU-B. Also serves as the input to an external current-range buffer for PMU-B. PMU-B Range E Resistor Connection PMU-B Range D Resistor Connection PMU-B Range C Resistor Connection PMU-B Range B Resistor Connection PMU-B Range A Resistor Connection PMU-B Sense Input. A Kelvin connection to the DUT. Provides the feedback signal in FVMI mode and the measured signal in FIMV mode for PMU-B. PMU-B Compensation Capacitor Connection 1. Provides compensation for the PMU-B main amplifier. PMU-B Compensation Capacitor Connection 2. Provides compensation for the PMU-B main amplifier. PMU-B Current-Range Sense-Resistor Connection. Connects to the external current-range sense resistor on the DUT side for PMU-B. See Figure 5. PMU-B Current-Range Sense-Resistor Connection. Connects to the external current-range sense resistor on the amplifier side for PMU-B. See Figure 5. Chip-Select Input. Force CS low to enable communication with the serial port. Serial Port Load Input. A logic low asynchronously loads data from the input registers into the PMU registers. Serial Clock Input Serial Data Input. Data loads into DIN MSB first. PMU-B Window-Comparator High-Comparator Output. A sense-B voltage above the VTHMAXB level forces the DUTHB output low. DUTHB is an open-drain output. PMU-B Window-Comparator Low-Comparator Output. A sense-B voltage below the VTHMINB level forces the DUTLB output low. DUTLB is an open-drain output. Digital Ground Serial Data Output. Provides data out from the shift register. Facilitates daisy-chaining to DIN of a downstream PMU. DOUT clocks out data MSB first. Logic Supply Voltage Input. The voltage applied at VL sets the upper logic-voltage level. PMU-A Window-Comparator Low-Comparator Output. A sense-A voltage below the VTHMINA level forces the DUTLA output low. DUTLA is an open-drain output. FUNCTION
MAX9949/MAX9950
RBCOM RBE RBD RBC RBB RBA
FORCEB PMU-B Driver Output. Forces a current or voltage to the DUT for PMU-B. SENSEB CC1B CC2B RXDB RXAB CS LOAD SCLK DIN DUTHB DUTLB
EXTBSEL PMU-B External Current-Range Selector. Selects the external current range for PMU-B. DGND DOUT VL
EXTASEL PMU-A External Current-Range Selector. Selects the external current range for PMU-A. DUTLA
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
Pin Description (continued)
PIN MAX9950 30 31 32 35 36 37 38 39 40 41 42 43 44 45 46 MAX9949 51 50 49 46 45 44 43 42 41 40 39 38 37 36 35 NAME DUTHA HI-ZB HI-ZA RXAA RXDA CC2A CC1A SENSEA FUNCTION PMU-A Window-Comparator High-Comparator Output. A sense-A voltage above the VTHMAXA level forces the DUTHA output low. DUTHA is an open-drain output. PMU-B MSRB Output State Control. A logic low places the MSRB output in a high-impedance state. PMU-A MSRA Output State Control. A logic low places the MSRA output in a high-impedance state. PMU-A Current-Range Sense-Resistor Connection. Connects to the external current-range sense resistor on the amplifier side for PMU-A. See Figure 5. PMU-A Current-Range Sense-Resistor Connection. Connects to the external current-range sense resistor on the DUT side for PMU-A. See Figure 5. PMU-A Compensation Capacitor Connection 2. Provides compensation for the PMU-A main amplifier. PMU-A Compensation Capacitor Connection 1. Provides compensation for the PMU-A main amplifier. PMU-A Sense Input. A Kelvin connection to the DUT. Provides the feedback signal in FVMI mode and the measured signal in FIMV mode for PMU-A. PMU-A Range A Resistor Connection PMU-A Range B Resistor Connection PMU-A Range C Resistor Connection PMU-A Range D Resistor Connection PMU-A Range E Resistor Connection PMU-A Range-Setting-Resistor Common Connection. Connect to one end of all range-setting resistors (RA_) for PMU-A. Also serves as the input to an external current range buffer for PMU-A. PMU-A Window-Comparator Upper Threshold Voltage Input. Sets the upper voltage threshold for the PMU-A window comparator. PMU-A Window-Comparator Lower Threshold Voltage Input. Sets the lower voltage threshold for the PMU-A window comparator. PMU-A Upper Clamp Voltage Input. Sets the upper clamp voltage level for PMU-A. PMU-A Lower Clamp Voltage Input. Sets the lower clamp voltage level for PMU-A. Input Voltage 0 for PMU-A. Sets the forced current in FI mode or the forced voltage in FV mode for PMU-A. Input Voltage 1 for PMU-A. Sets the forced voltage in FV mode or the forced current in FI mode for PMU-A. PMU-A Measurement Output. Provides a voltage equal to the SENSE voltage in FIMV mode and provides a voltage proportional to the DUT current in FVMI mode for PMU-A. Force HI-ZA low to place MSRA in a high-impedance state. Offset Voltage Input. Sets an offset voltage for the internal current-sense amplifier for both PMU-A and -B.
FORCEA PMU-A Driver Output. Forces a current or voltage to the DUT for PMU-A. RAA RAB RAC RAD RAE RACOM
49 50 51 52 53 54
32 31 30 29 28 27
THMAXA THMINA CLHIA CLLOA IN0A IN1A
55
26
MSRA
56
25
IOS
10
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Dual Per-Pin Parametric Measurement Units
Pin Description (continued)
PIN MAX9950 57 58 MAX9949 24 23 NAME AGND MSRB Analog Ground PMU-B Measurement Output. Provides a voltage equal to the SENSE voltage in FIMV mode and provides a voltage proportional to the DUT current in FVMI mode for PMU-B. Force HI-ZB low to place MSRB in a high-impedance state. Input Voltage 1 for PMU-B. Sets the forced voltage in FV mode or the forced current in FI mode for PMU-B. Input Voltage 0 for PMU-B. Sets the forced current in FI mode or the forced voltage in FI mode for PMU-B. PMU-B Lower-Clamp Voltage Input. Sets the lower clamp voltage level for PMU-B. PMU-B Upper-Clamp Voltage Input. Sets the upper clamp voltage level for PMU-B. PMU-B Window-Comparator Lower Threshold Voltage Input. Sets the lower voltage threshold for the PMU-B window comparator. PMU-B Window-Comparator Upper Threshold Voltage Input. Sets the upper voltage threshold for the PMU-B window comparator. FUNCTION
MAX9949/MAX9950
59 60 61 62 63 64
22 21 20 19 18 17
IN1B IN0B CLLOB CLHIB THMINB THMAXB
Detailed Description
The MAX9949/MAX9950 force or measure voltages in the -2V to +7V through -7V to +13V ranges, dependent upon the supply voltage range (V CC and V EE ). However, the devices can handle supply voltages up to +30V (VCC to VEE) and a 20V DUT voltage swing at full current. The MAX9949/MAX9950 PMU also force or measure currents up to 25mA, with a lowest full-scale range of 2A. Use an external buffer amplifier for current ranges greater than 25mA. The MSR_ output presents a voltage proportional to the measured voltage or current. Place MSR_ in a low-leakage, high-impedance state by pulling HI-Z_ low. Integrated comparators with externally programmable voltage thresholds provide "too low" (DUTL_) and "too high" (DUTH_) voltage-monitoring outputs. Each comparator output features a selectable high-impedance state. The devices feature separate FORCE_ and SENSE_ connections and are fully protected against short circuits. The FORCE_ output has two voltage clamps, negative (CLLO_) and positive (CLHI_), to limit the voltage to externally provided levels. Two control voltage inputs, selected independently of the PMU mode, allow for greater flexibility.
Once the input data register fills, the data becomes available at DOUT MSB first. This data output allows for daisy-chaining multiple devices. Figures 1, 2, and 3 show the serial interface timing diagrams.
Serial Port Speed
The serial port timing specifications are measured at a logic supply voltage (VL) of +3.0V, ensuring operation of the serial port at rated speed for VL from +3.0V to +5.5V. The serial interface has two ranks. Each PMU has an input register that loads from the serial port shift register. Each PMU also has a PMU register that loads from the input register. Data does not affect the PMU until it reaches the PMU register. This register configuration permits loading of the PMU data into the input register at one time and then latching the input register data into the PMU register later, at which time the PMU function changes accordingly. The register configuration also provides the ability to change the state of the PMU asynchronously with respect to the loading of that PMU's data into the serial port. Thus, the PMU easily updates simultaneously with other PMUs or other devices. Use the LOAD input to asynchronously load all input registers into the PMU registers. If LOAD remains low when data latches into an input register, the data also transfers to the PMU register.
Serial Interface
The MAX9949/MAX9950 use a standard 3-wire SPITM/QSPITM/MICROWIRETM-compatible serial port.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
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11
Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
Functional Diagram
TO EXTERNAL CURRENT BOOSTER FOR HIGHEST RANGE RXA_ RXD_ CX RD EXTSEL_ RC RE
CLHI_
CLLO_
RB CCM RA
CC1_
VCC IN1_
VEE 1
CC2_
R_COM
R_A
R_B
R_C
R_D
R_E
RANGE RESISTOR SELECT IN0_ FORCE_ 0
HI-ZFORCE_
INMODE_
CLENABLE_
IOS CS SCLK LOAD DIN DOUT VL
RS0_ RS1_ RS2_ SERIAL INTERFACE 10 TO OTHER PMU CHANNEL FMODE_ MMODE_ 0 1
HI-Z_
RFS*
HI-ZMEAS_
0 MSR_ DISABLE_ THMAX_ DUTH_ MAX9949 MAX9950 DUTL_ THMIN_ AGND DGND 1 SENSE_
*RFS INTERNAL TO MAX9949D/MAX9950D ONLY
12
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
CS INPUT REGISTER(S) UPDATED
SCLK
DIN
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Q15 FIRST BIT FROM PREVIOUS WRITE
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
LAST BIT FROM PREVIOUS WRITE
LOAD
PMU REGISTERS UPDATED
Figure 1. Serial Port Timing with Asynchronous Load
CS INPUT AND PMU REGISTER(S) UPDATED
SCLK
DIN
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Q15 FIRST BIT FROM PREVIOUS WRITE
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
LAST BIT FROM PREVIOUS WRITE
LOAD LOAD = 0
Figure 2. Serial Port Timing with Synchronous Load
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
tCH
SCLK
tCSSO tCSHO
tCL tCSH1
tCSS1
CS tDH tCSWH
tDS
DIN
D15
D14
D13
D12
D11
D10
D1
D0
DOUT
D15last
D14last
D13last
D12last
D11last tDO
D10last
D1last
D0last
tLDW LOAD
Figure 3. Detailed Serial Port Timing Diagram
CS SCLK DIN 6
SHIFT REGISTER /16 10
DOUT
CONTROL DECODE
INPUT REGISTER A
INPUT REGISTER B 10 PMU REGISTER B
10 PMU REGISTER A
LOAD
TO PMUA
TO PMUB
Figure 4. Dual PMU Serial Port Block Diagram
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
Table 1. Bit Order
BIT 15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) BIT NAME INMODE FMODE MMODE RS2 RS1 RS0 CLENABLE HI-ZFORCE HI-ZMSR DISABLE Don't care Don't care A2 A1 C2 C1 1 1 1 0
Table 2. Address Bit
(BIT 3) A2 0 0 1 1 (BIT 2) A1 0 1 0 1 OPERATION Do not update any input register (NOP). Only update input register A. Only update input register B. Update both input registers with the same data.
Table 3. Control Bit
(BIT 1) C2 0 0 (BIT 0) C1 0 1 OPERATION Data stays in input register. Transfer PMU-A input register to PMU register. Transfer PMU-B input register to PMU register. Transfer both input registers to the PMU registers.
Bit Order
The MAX9949/MAX9950 use the bit order, MSB first in and first out, as shown in Table 1.
PMU Control
Programming both PMUs with the same data requires a 16-bit word. Programming each PMU with separate data requires two 16-bit words. The address bits specify which input registers the shift register loads. Table 2 describes the function of the address bits. Bits (C2, C1) specify how the data loads into the second rank PMU registers. These two control bits serve a similar function as the LOAD input. The specified actions occur when CS goes high, whereas the LOAD input loads the PMU register anytime. When either C2 or C1 is low, the corresponding PMU register is transparent. Table 3 describes the function of the two control bits. The NOP operation requires A1 = A2 = C1 = C2 = 0. In this case, the data transfers through the shift register without changing the state of the MAX9949/MAX9950. C1 = C2 = 0 allows for data transfer from the shift register to the input register without transferring data to the PMU register (unless the LOAD input is low). This per-
mits the latching of data into the PMU register at a later time by the LOAD input or subsequent command. Table 4 summarizes the possible control and address bit combinations. When asynchronously latching only one PMU's data, the input register of the other PMU maintains the same data. Therefore, loading both PMU registers would update the one PMU with new data while the other PMU remains in its current state.
Mode Selection
Four bits from the control word select between the various modes of operation. INMODE selects between the two input analog control voltages. FMODE selects whether the PMU forces a voltage or a current. MMODE selects whether the DUT current or DUT voltage is directed to the MSR_ output. HI-ZFORCE places the driver amplifier in a high-output impedance state. Table 5 describes the various force and measure modes of operation.
Current-Range Selection
Three bits from the control word, RS0, RS1, RS2, control the full-scale current range for either FI (force cur-
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15
Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
Table 4. PMU Operation Using Control and Address Bits
BIT (3:2) A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT (1:0) C2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NOP. Load PMU register B from input register B. Load PMU register B from input register B. NOP. NOP. Load PMU register B from input register B. Load PMU register B from input register B. Load input register B from shift register. Load input register B from shift register. Load input register B and PMU register B from shift register. Load input register B and PMU register B from shift register. Load input register B from shift register. Load input register B from shift register. Load input register B and PMU register B from shift register. Load input register B and PMU register B from shift register. PMU-B OPERATION PMU-A OPERATION
NOP: data just passes through. Load PMU register A from input register A. NOP. Load PMU register A from input register A. Load input register A from shift register. Load input register A and PMU register A from shift register. Load input register A from shift register. Load input register A and PMU register A from shift register. NOP. Load PMU register A from input register A. NOP. Load PMU register A from input register A. Load input register A from shift register. Load input register A and PMU register A from shift register. Load input register A from shift register. Load input register A and PMU register A from shift register.
Table 5. PMU Force/Measure Mode Selection
(BIT 15) IN MODE 0 1 0 1 0 1 0 1
X X
(BIT 14) F MODE 0 0 0 0 1 1 1 1
X X
(BIT 13) M MODE 0 0 1 1 0 0 1 1 0 1
(BIT 8) HI-ZFORCE 1 1 1 1 1 1 1 1 0 0
PMU MODE FVMI FVMI FVMV FVMV FIMI FIMI FIMV FIMV FNMV
FORCE OUTPUT Voltage Voltage Voltage Voltage Current Current Current Current HI-Z
MEASURE OUTPUT IDUT IDUT VDUT VDUT IDUT IDUT VDUT VDUT VDUT
ACTIVE INPUT VIN0 VIN1 VIN0 VIN1 VIN0 VIN1 VIN0 VIN1
X
FNMI--Meaningless mode
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
Table 6. Current Range Selection
(BIT 12) RS2 0 0 0 0 1 1 1 1 (BIT 11) RS1 0 0 1 1 0 0 1 1 (BIT 10) RS0 0 1 0 1 0 1 0 1 RANGE 2A 2A 20A 200A 2mA 25mA External 25mA NOMINAL RESISTOR VALUE R_E = 1M R_E = 1M R_D = 100k R_C = 10k R_B = 1k R_A = 80 -- R_A = 80
Table 7. Clamp Enable
CLENABLE 1 0 MODE Clamps enabled Clamps disabled
Table 8. MSR_ Output Truth Table
(BIT 7) HI-ZMSR 1 0 1 0 HI-Z_ 1 1 0 0 MSR_ STATE Measure output enabled High-Z High-Z High-Z
rent) or MI (measure current). Table 6 describes the full-scale current-range control.
Clamp Enable
The CL ENABLE bit enables the force-output voltage clamps when high and disables the clamps when low. Table 7 depicts the various clamp mode options.
serial data word 16.5 clock cycles later. This allows for daisy-chaining an additional device using DOUT and the same clock.
"Quick Load" Using Chip Select
If CS goes low and then returns high without any clock activity, the data from the input registers latch into the PMU registers. This extra function is not standard for SPI/QSPI/MICROWIRE interfaces. The quick load mimics the function of LOAD without forcing LOAD low.
Measure Output High-Impedance Control
The MSR_ output attains a low-leakage, high-impedance state by using the HI-ZMSR control bit or the HI-Z_ input. The 2 bits are logically ORed together to control the MSR_ output. The HI-Z_ input allows external multiplexing among several PMU MSR_ outputs without using the serial interface. Table 8 explains the various output modes for the MSR_ output.
Comparators
Two comparators configured as a window comparator monitor the MSR_ output. THMAX_ and THMIN_ set the high and low thresholds that determine the window. Both outputs are open drain and share a single disable control that places the outputs in a high-Z, low-leakage state. Table 9 describes the comparator output states of the MAX9949/MAX9950.
Digital Output (DOUT)
The digital output follows the last output of the serial shift register and clocks out on the falling edge of the input clock. DOUT provides the first bit of the incoming
Table 9. Comparator Truth Table
(BIT 6) DISABLE 0 1 1 1 1 CONDITION X VMSR > VTHMAX and VTHMIN VTHMAX > VMSR > VTHMIN VTHMAX and VTHMIN > VMSR VTHMIN > VMSR > VTHMAX* DUTH_ High-Z 0 1 1 0 DUTL_ High-Z 1 1 0 0
*VTHMAX > VTHMIN constitutes normal operation. This condition, however, has VTHMIN > VTHMAX and does not cause any problems with the operation of the comparators.
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17
Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
ing +4V to IOS forces the voltage range that corresponds to full-scale current from 0 to +8V. The following equations determine the minimum and maximum currents for each current range corresponding to the input voltage or measure voltage: VMAXCURRENT = VIOS + 4V VMINCURRENT = VIOS - 4V Choose IOS so the limits of the MSR_ output do not go closer than 2.8V to either VEE or VCC. For example, with supplies of +10V and -5V, limit the MSR_ output to -2.2V and +7.2V. Therefore, set IOS between +1.8V and +3.2V. The MSR_ output could clip if IOS is not within this range. Use these general equations for the limits on IOS: Minimum VIOS = VEE + 6.8V Maximum VIOS = VCC - 6.8V
Applications Information
In force-voltage (FV) mode, the output FORCE_ voltage is directly proportional to the input control voltage. In force-current (FI) mode, the current flowing out of the FORCE_ output is proportional to the input control voltage. Positive current flows out of the PMU. In force-nothing (FN) mode, the FORCE_ output is high impedance. In measure-current (MI) mode, the voltage at the MSR_ output is directly proportional to the current exiting the FORCE_ output. Positive current flows out of the PMU. In measure-voltage (MV) mode, the voltage at the MSR_ output is directly proportional to the voltage at the SENSE_ input.
Current-Sense-Amplifier Offset Voltage Input
IOS is a buffered input to the current-sense amplifier. The current-sense amplifier converts the input control voltage (IN0_ or IN1_) to the forced DUT current (FI) AND converts the sensed DUT current to the MSR_ output voltage (MI). When IOS equals zero relative to DUTGND (the GND voltage at the DUT, which the level-setting DACs and the ADC are presumed to use as a ground reference), the nominal voltage range that corresponds to full-scale current is -4V to +4V. Any voltage applied to the IOS input adds directly to this control input/measure output voltage range, i.e., apply-
Current Booster for Highest Current Range
An external buffer amplifier can be used to provide a current range greater than the MAX9949/MAX9950 maximum output current (Figure 5). This function operates as follows. A digital output decoded from the range select bits, EXTSEL_, indicates when to activate the booster. The R_COM output serves as an input to an external buffer through a 50 current-limit series resistor. Each side of the external current-sense resistor feeds back to RXA_ and RXD_. Ensure that the buffer circuit enters a high-Z output state when not selected. Any leakage in the buffer adds to the leakage of the PMU.
Voltage Clamps
50 REXTBOOST FORCE_
The voltage clamps limit the FORCE_ output and operate over the entire specified current range. Set the clamp voltages externally at CLHI_ and CLLO_. The voltage at the FORCE_ output triggers the clamps independent of the voltage at the SENSE_ input. When enabled, the clamps function in both FI and FV modes.
Current Limit
R_COM EXTSEL_ RXA_ RXD_
AV = +2
The current-limiting circuitry on the FORCE_ output ensures a well-behaved MSR_ output for currents between the full current range and the current limits, i.e., for currents greater than the full-scale current, the MSR_ voltage is greater than +4V and for currents less than the full-scale current, the MSR_ voltage is less than -4V.
INTERNAL TO MAX9949/MAX9950
Independent Control of the Feedback Switch and the Measure Switch
Two single-pole-double-throw (SPDT) switches determine the mode of operation of the PMU. One switch
Figure 5. External Current Boost
18
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
IN1_
RSENSE
IN1_ FORCE_
RSENSE
FORCE_
DUT DUT AV = +2 SENSE_ DUTGND AV = +2 SENSE_ DUTGND
MSR_
MSR_
Figure 6. Force-Voltage/Measure-Current Functional Diagram
Figure 7. Force-Current/Measure-Voltage Functional Diagram
determines whether the sensed DUT current or DUT voltage feeds back to the input (sensing), and thus determines whether the MAX9949/MAX9950 force current or voltage. The other switch determines whether the MSR_ output senses the DUT current or DUT voltage. Independent control of these switches and the HI-ZFORCE state permits flexible modes of operation beyond the traditional force-voltage/measure-current (FVMI) and force-current/measure-voltage (FIMV) modes. The MAX9949/MAX9950 support the following five modes: * FVMI * FIMV * FVMV * FIMI * FNMV Figure 6 shows the internal path structure for force-voltage/measure-current mode. In force-voltage/measurecurrent mode, the current across the appropriate external sense resistor (R_A to R_E) provides a voltage to the MSR_ output. The SENSE_ input samples the voltage at the DUT and feeds the buffered result back to the negative input of the voltage amplifier. The voltage at MSR_ is proportional to the FORCE_ current in accordance with the following formula: VMSR_ = IFORCE_ x RSENSE x 2 Figure 7 shows the internal path structure for the forcecurrent/measure-voltage mode. In force-current/measure-voltage mode, the appropriate external sense resistor (R_A to R_E) provides a feedback voltage to the inverting input of the voltage amplifier. The SENSE_
input samples the voltage at the DUT and provides a buffered result at the MSR_ output.
High-Z States
The FORCE_, MSR_, and comparator outputs feature individual high-Z control that places them into a highimpedance, low-leakage state. The high-Z state allows busing of MSR_ and comparator outputs with other PMU measure and comparator outputs. The FORCE_ output high-Z state allows for additional modes of operation as described in Table 5 and can eliminate the need for a series relay in some applications. The FORCE_, MSR_, and comparator outputs power up in the high-Z state.
Input Source Selection and Gating
Either one of two input signals, IN0_ or IN1_, can control both the forced voltage and the forced current. In this case, the two input signals represent alternate forcing values that can be selected with the serial interface. Alternatively, each input signal can be dedicated to control a single forcing function (i.e., voltage or current).
Ground, DUT Ground, IOS
The MAX9949/MAX9950 utilize two local grounds, AGND (analog ground) and DGND (digital ground). Connect AGND and DGND together on the PC board. In a typical ATE system, the PMU force voltage is relative to the DUT ground. In this case, reference the input voltages IN0_ and IN1_ to the DUT ground. Similarly, reference IOS to the DUT ground. If it is not desired to offset the current control and measure voltages, connect IOS to the DUT ground potential. Reference the MSR_ output to the DUT ground.
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Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
VDUT VEE - 3.5V VEE - 5V
3) Variations in the power supplies--system implementation determines the variance 4) Variation of DUT ground vs. PMU ground--system implementation determines the variance Neglecting the effects of the third and fourth items, Figure 8 demonstrates the force output capabilities of the PMU.
IDUT
VEE + 5V VEE + 3.5V IMIN IMIN
Figure 8 indicates that, for zero DUT current, the DUT voltage swings from (VEE + 3.5V) to (VCC 3.5V). For larger positive DUT currents, the positive swing drops off linearly until it reaches (VCC - 5V) at full current. Similarly, for larger negative DUT currents, the negative voltage swing drops off linearly until it reaches (VEE + 5V) at full current.
Figure 8. PMU Force Output Capability
Settling Times and Compensation Capacitors
The data in the Electrical Characteristics table reflects the circuit shown in the block diagram that includes a single compensation capacitor (Cx) effectively across all the sense resistors. Placing individual capacitors, CRA, C RB, C RC, C RD, and C RE directly across the sense resistors, R_A, R_B, R_C, R_D, and R_E, independently optimizes each range. The combination of the capacitance across the sense resistors (Cx or CRA, CRB, CRC, CRD, and CRE) and the main amplifier compensation comparator, CCM, ensures stability into the maximum expected load capacitance while optimizing settling time.
Short-Circuit Protection
The FORCE_ output and SENSE_ input can withstand a short to any voltage between the supply rails.
Mode and Range Change Transients
The MAX9949/MAX9950 feature make-before-break switching to minimize glitches. The integrated voltage clamps also reduce glitching on the output.
DUT Voltage Swing vs. DUT Current and Power-Supply Voltages
Several factors limit the actual DUT voltage that the PMU delivers: 1) The overhead required by the amplifiers and other integrated circuitry--this is typically 3.5V from each rail for no load current and 5V under full load 2) The voltage drop across the current-range select resistor and internal circuitry in series with the sense resistor--at full current, the combined voltage drop is typically 2.75V
Digital Inputs (SCLK, DIN, CS, LOAD)
The digital inputs incorporate hysteresis to mitigate issues with noise, as well as provide for compatibility with opto-isolators that can have slow edges.
Chip Information
PROCESS: BiCMOS
20
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Dual Per-Pin Parametric Measurement Units
MAX9949 Pin Configuration
EXTBSEL EXTASEL DUTHB DGND DGND DOUT DUTHA DUTLB DUTLA LOAD HI-ZB HI-ZA SCLK
MAX9949/MAX9950
CS
DIN
64
63
62
61
60
59
58
57
56
55
VL
54
53
52
51
50
49
VEE VCC RXAB RXDB CC2B CC1B SENSEB FORCEB RBA
1 2 3 4 5 6 7 8 9
+
48 VEE 47 VCC 46 RXAA 45 RXDA 44 CC2A 43 CC1A 42 SENSEA 41 FORCEA
MAX9949
40 RAA 39 RAB 38 RAC 37 RAD 36 RAE 35 RACOM 34 VCC 33 VEE
RBB 10 RBC 11 RBD 12 RBE 13 RBCOM 14 VCC 15 VEE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
______________________________________________________________________________________
THMAXB
THMAXA
THMINB
THMINA
CLLOB
CLLOA
CLHIB
CLHIA
MSRB
MSRA
AGND
IN0B
IN1B
IN1A
IN0A
IOS
21
Dual Per-Pin Parametric Measurement Units MAX9949/MAX9950
MAX9950 Pin Configuration
THMAXB THMINB CLLOB CLLOA CLHIB MSRB AGND MSRA CLHIA THMINA
50
IN0B
IN1B
64
63
62
61
60
59
58
57
56
IOS
55
54
IN1A
53
IN0A
52
51
49
VEE VCC RBCOM RBE RBD RBC RBB RBA FORCEB
1 2 3 4 5 6 7 8 9
+
THMAXA
48 VEE 47 VCC 46 RACOM 45 RAE 44 RAD 43 RAC 42 RAB 41 RAA 40 FORCEA 39 SENSEA 38 CC1A 37 CC2A 36 RXDA 35 RXAA 34 VCC 33 VEE 32
MAX9950
SENSEB 10 CC1B 11 CC2B 12 RXDB 13 RXAB 14 VCC 15 VEE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EXTBSEL
SCLK
HI-ZB
DUTHB
DUTLB
DUTLA
EXTASEL
DUTHA
LOAD
DOUT
DGND
DGND
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 64 TQFP-EPR 64 TQFP-EP PACKAGE CODE C64E-9R C64E-6 DOCUMENT NO. 21-0162 21-0084
22
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HI-ZA
DIN
CS
VL
Dual Per-Pin Parametric Measurement Units
Revision History
REVISION NUMBER 2 REVISION DATE 3/09 DESCRIPTION Corrected timing diagrams and changed to lead-free package. PAGES CHANGED 1, 13, 14
MAX9949/MAX9950
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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